1. Field of Invention
This invention is directed to a method for failure mode analysis and more particularly to a method of removing a low dielectric constant material in preparation for failure mode analysis in the manufacture of integrated circuits.
2. Description of Related Art
In the manufacture of integrated circuits, failure mode analysis is an important tool for improving the manufacturing process. One important process is the fabrication of metal lines. In failure mode analysis of this process, it is necessary to check the surface of the metal film in order to check for voiding at the metal surface and it is also necessary to check the cross-section to check for voiding in the via hole. Copper damascene metallization has become very popular in integrated circuit fabrication. Copper is deposited within a damascene opening and then polished such as by chemical mechanical polishing (CMP) to leave the copper only within the opening. For well-controlled copper CMP performance, dummy metal lines are added in every metal layer for 90 nm and below geometry. This increases the difficulty of failure mode analysis since the metal cannot be removed by dry etching. The conventional method to prepare a wafer for failure mode analysis is to use wet etching to remove the intermetal dielectric layer (IMD) and then to use ACE vibration to remove the metal.
As devices shrink to 90 nm or below, it is desirable to use ultra low dielectric constant (k) dielectric material (k<4.5 and preferably less than 3.0) as the IMD layer in order to reduce Rc delay. However, these ultra low-k films are difficult to remove using the current wet etch solution. It is desired to find a method to easily remove the ultra low-k films for failure mode analysis. Also, as devices shrink to 90 nm or below and using ultra low dielectric constant material as the IMD layer, the adhesion between conductive materials and the low dielectric constant materials is not sufficient for integrated circuit usage. Therefore, an optimized surface roughness of the low dielectric constant material before filling conductive material is crucial, especially for thermal stress release and electron migration issues.
U.S. Pat. No. 6,596,467 to Gallagher et al describes a low-k dielectric material having a removable porogen. The porogen is removed after metal planarization.
The papers “Surface roughness and surface-induced resistivity of gold films on mica: influence of the theoretical modelling of electron-surface scattering” by Ra'ul C. Munoz et al, J. Phys.: Condens. Matter 12 (2000) L379–L385; “Increase in Electrical Resistivity of Copper and Aluminum Fine Lines” by Yuko Hanaoka, et al, Materials Transactions, Vol. 43, No 7 (2002) pp. 1621–1623; and “Polyetheretherketone (PEEK) Surface Functionalization by Low-Energy Ion-Beam Irradiation under a Reactive O2 Environment and Its Effect on the PEEK/Copper Adhesives” by and Sehyun Kim, Ki-Jun Lee, and Yongsok Seo, Langmuir, 20 (1), 157–163, 2004 discuss a roughened surface as important for a compromised adhesive capability and the resistance of the conductor layer.